| Intel’s latest chip innovations include a new rapid design where the tiled–design approach allows designers to use smaller cores that can easily be repeated across the chip. A single–core chip of this size (100 million transistors) would take roughly twice as long and twice as many people to design. Each of these smaller cores contain a 5-port messaging passing router, which are connected in a 2D mesh-type network that implements the passing of messages. This mesh interconnect scheme could replace the multi-core chip interconnects that currently exist, allowing for better communications between the cores, using less power. Depending on the requirements of the user, the individual engines and data routers of each core can be activated or deactivated. According to Intel, power consumption is another area of improvement, with 1 teraflop requiring just 62 watts, less than many other desktop processors. Although the test chip is not for sale just yet, it could make for a faster-future in the processor world within the next few years. |